Must have coursework, project background, or experience in the followingbr 1. RTL coding in Verilog and VHDL;br 2. FPGA or ASIC design process and tool flow, including synthesis, placebr and route algorithms;br 3. Vivado software;br 4. Design methodologies for timing closure and runtime reduction;br 5. VLSI design including FPGA design; and,br 6. FPGA architectures.br br Employer will accept alternate combination of education and experience Bachelors degree or foreign equivalent in Electrical Engineering, Computer Engineering, or a related field and three 3 years of experience in an engineering or industrial product manufacturing related occupation. Employer will accept any suitable combination of education, training, or experience.
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