Must have coursework or prior work experience in each of the followingbr 1. System Verilog based verification environment and development using UVM Universal Verification Methodology;br 2. Debug using industry standard simulation tools including Synopsyss VCS, Cadences IES or Mentors Questa;br 3. Verification planning, implementation, coverage analysis, data management, and revision control; andbr 4. DRAM Memory Controller standards and protocols including DDR, LPDDR, QDR, HBM, or RLDRAM.br br Employer will accept alternate combination of education and experience Masters degree or foreign equivalent in Electronic Engineering, Electrical Engineering, Computer Engineering, Computer Science or related field. Employer will accept any suitable combination of education, training, or experience.

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