Requires Masters degree or foreign equivalent degree in Computer Engineering, ElectricalElectronics Engineering, Computer Science or a related field plus six 6 months experience evaluating and supporting static verification EDA tools, methodologies and flows. Education andor experience must include 1. CDC, Lint, RDC, and Constraints static verification EDA tools; 2. VerilogVHDL; 3. ASIC design fundamentals; 4. Customerfacing EDA tools support; 5. Scripting languages; and 6. Creating and delivering technical presentations to customers.

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