STMICROELECTRONICS, INC. – $108,701.00/Year

Requires a Masters Degree, or foreign equivalent degree in Electrical Engineering or Computer Software Engineering and three 3 years of experience in the job offered or three 3 years of experience developing UVM component sequences, drivers, monitors, agents, scoreboards, and register maps; completing design specifications, writing test plans and ensuring exhaustive verification; developing UVM components such as sequences, drivers, monitors, agents, scoreboards, and registering maps to perform constrained random functional verifications at block level and system level; utilizing SystemVerilog, Verilog HDL, Perl, and shell scripting; and utilizing RTL simulators Cadence NCVerilog, Simvision, and ModelSim.br br Employer will accept any suitable combination of education, training, or experience.