exp. must be progressive include Exp. must include digital logic design; simulation, LINT, logic equivalency checking, clock domain cross checking, synthesis, static timing analysis, DFT support; ASIC SoC development flow; Verilog; C or C; scripting languages, VCS compiler, Synopsys Cadence EDA tools; FPGA simulation; written and oral reportspresentations. Will accept any suitable combination of education, training or experience.

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