Employer will accept a Masters degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2 years of work experience in job offered or in an engineeringrelated occupation.br Experience must include 6 months of experience in the followingbr 1. RTL Synthesis and design optimization for Power, Performance, Area;br 2. Frontend and backend ASIC tools;br 3. RTL design using SystemVerilog or other HDL;br 4. Managing multiple design releases and working with crossfunctional teams to support and debug timing, area, power issues;br 5. EDA tools and scripting languages Python, Tcl used to build tools and flows for complex environments;br 6. ASIC and Systems Development;br 7. TimingPhysical libraries, SRAM Memories; andbr 8. Clock Domain Crossing, Reset Domain Crossing, LEC verification.
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