MEDIATEK USA INC. – $124,654.00/Year

1. Must have experience in latest DV methodologies System Verilog and UVM, AssemblyCbased Verification; 2. Must have Experience in developing a DV plan based on Functional Specification, build the necessary test benchinfrastructure, develop tests and verify design; 3. Must be able to develop and deploy new DV methodologies; 4 Must possess strong debugging skills and familiar with using industry standard simulation e.g. VCS and debug tools; and 5. Must possess strong ARM CPU knowledge and scripting skills in Perl and Csh.