Bachelors or foreign equivalent degree in Computer Science, ElectricalComputer Engineering, or a related field and five 5 years of experience in the job offered or related occupation.br br Experience must include five 5 years with each of the followingbr br 1. Maintaining, enhancing, and supporting place and route, timing andor integration flows incorporating industry standard EDA tools.br 2. Performing synthesis, floor plan, place, and route, analyze timing, and close on complex logic blocks.br 3. Developing and implementing timing and logic ECOs.br 4. Interfacing with the RTL design team to drive design modifications to resolve congestion and timing issues.br 5. Working with the global timing team in debuggingresolving any block level timing issues seen at the IP level.br 6. Testing and maintaining chip endtoend flows, with specific focus on place and route, integration, and timing.br 7. Interfacing with tool vendors to drive tool fixes and improvements in support of ongoing and planned CAD activities.br 8. Deliver tapeout quality place and route blocks for inclusion in partitions.
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