Masters or foreign equivalent degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and two 2 years of experience in the job offered or related occupation.br br Experience must include two 2 years with each of the followingbr br 1. RTL design with Hardware Description Language Verilog, SystemVerilog.br 2. RTL simulations, synthesis, timing analysis and verification.br 3. Waveform analysis and debugging tools e.g. Synopsys Verdi.br 4. Performing Lint, CDC check, Timing closure, coverage closure analysis.br 5. Design performance and power analysis with Hspice simulations.br 6. Implementing IP microarchitecture to meet performance, timing, and power targets.br 7. ASIC design methodologies for clock domain checks and reset checks.br 8. Debugging silicon issues and finding root cause.

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