Requires a Masters degree or foreign equivalent in Electrical Engineering or a related field with concentrated coursework in superconductor integrated circuits. Must have the following skills from academic coursework or industry Design of Integrated Circuits in Cadence Virtuoso and Synopsys Custom Compiler. Simulating the functional behavior of Digital Integrated Circuits, its timing, operating margins using industry standard simulators including Cadence Spectre and Synopsys Primesim; Design and Validation of Integrated Circuit Design using hardware descriptive languages HDL; Physical layout of Integrated Circuit Design including its verification such as Design Rule Checker DRC and Layout vs Schematic LVS using Cadence Synopsys Integrated Circuits IC Verification tools. Performing Static Timing Analysis STA on digital circuits for timing verification. Performing Synthesis of Register Transfer Level codes and Automated placement and routing of Digital Circuits. Tapeout of Integrated Circuit Chips.
Categories: eb3
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