PhD in Electrical or Computer Engineering or Related and 3 years of research experience in designing, fabricating glass based advanced semiconductor packaging technologies for heterogenous integration, including experience in single multichip package architectures, transmission line theory and signal integrity modeling; EM simulation of interconnects, passives and module design, cleanroom fabrication processes, including RDL redistribution layer technologies like photolithography, Copper metallization, buildup layer lamination, via formation, surface finish, BGA ball grid array balling and chip board level assembly, underfilling, reliability testing, and failure analysis.
Categories: eb3
0 Comments