Minimum Requirements Masters degree in Electrical Engineering, Electronic Engineering, or related field, plus seven 7 years of experience in the job offered, or in a related engineering occupation.br br Position Requiresbr br 1. Physical implementation of system on chip SoC design, including floorplan, placement, clock synthesis, route, and timing closure;br 2. Semiconductor manufacturing foundry design rules and flow, including 3nm, 5nm,7nm, 14 nm, 28nm, and 40nm design flow experience;br 3. Cadence place and route tools, including Innovus;br 4. Cadence timing and power analysis tools, including Tempus, voltus, and Quantus;br 5. Cadence physical verification tools, including PVS or Pegasus;br 6. Digital Logic Design;br 7. TCL Scripting language; andbr 8. Linux OS commands and C shell scripting.br br Must be available to work on projects at various, unanticipated sites throughout the United States.
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