Must have 3 years of experience in the followingbr br Verilog, System Verilog, or VHDL;br C, C, or Python;br Perl, TCL, or Shell;br Computer Architecture or VLSI design; andbr RTL verification and optimization, RTL simulations, coherence protocols, interconnect and memory system design, or design flowsmethodologies for chip verification.br br Employer will accept alternate combination of education and experience Bachelors degree in an accepted degree field and five 5 years of progressive, postbaccalaureate experience in job offered or closely related engineering role.br br Employer will accept any suitable combination of education, training, or experience.

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