Bachelors degree in Electrical, Computer, or Electronics Engineering, or a related field and 6 years of industry experience in digital and mixed signal verification. 6 years of experience to include Functional and code coverage and mixed signalanalog modeling for verification; Gate level simulation; Regression methodology and creation of test plans; System VerilogUVM; and EDA Verification Tools Cadence or Synopsys. 5 years of experience to include Scripting experience in PERL, TCL or Python programming languages; and formal verification. 3 years of experience to include leading digital or mixed signal SOC verification projects.

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