SPECIAL REQUIREMENTS Skills with the following requiredbr 1. digital circuit design flow and VerilogSystemVerilog RTL languages;br 2. documenting design specifications and working with FEBE design teams to realize lowpower features and meet tapeout signoff requirements; andbr 3. designing the testing plan for digital IPs and providing validation plan to quantify silicon performance gain.br br EDUCATION Bachelors degree or foreign equivalent in Computer Science, Electrical Engineering, Electronic Engineering, or related field.br br EXPERIENCE Six 6 years of progressively responsible postbaccalaureate work experience as a principal engineer, as an engineer, or related occupation.
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