Must have 2 years of experience in the followingbr Verilog, System Verilog, or VHDL;br Python, C, or C;br Perl, TCL, or Shell;br ASIC Design;br Unix, Linux, or realtime operating systems;br RTL design and coding; andbr Design flows and methodologies used for chip verification.br br Skills may be gained concurrently.br br Employer will accept alternate combination of education and experience Bachelors degree in an accepted degree field and five 5 years of progressive, postbaccalaureate experience in job offered or closely related engineering role.br br Employer will accept any suitable combination of education, training, or experience.

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