Masters or foreign equivalent degree in Electrical Engineering, Computer Science, Electronic Engineering, or a related field and five 5 years of experience in the job offered or related occupation.br br Experience must include Five 5 years of experience withbr 1. Utilize Verilog, and MATLAB to model and simulate circuits.br 2. Evaluate intermediate and final results of projects during the design phase and during silicon evaluation, to ensure accomplishment of technical objectives.br 3. Provide guidance to physical designers and monitor the progress of IC layout.br 4. Collaborate with Design Verification teams to complete verifications of analogdigital interface functions.br 5. Collaborate with validation, product engineering, and test engineering teams to enable successful transfer to production.br 6. Experience using Cadence Spectre and simulation tools AFS, ADE, ADEXL.br 7. Post Layout Extraction tool and use of Config View within Cadence to run multiblock simulations with schematic and extracted netlist as well as functional and VerilogA views.
Categories: eb3
0 Comments