Bachelors or foreign equivalent degree in Computer Science, Engineering, Math, Information Systems, Physics or related. 60 months of experience in any engineering related occupation. Experience must include 12 months experience in System Verilog, developing stimulus and checkers to uncover bugs, developing a layered testbench using System Verilog and UVM to verify digital designs, developing functional coverage models using System Verilog covergroups, driving verification closure through constrained random testcases, Writing Verification Plans, and UNIX.

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