Masters or foreign equivalent degree in ElectricalElectronic Engineering, Computer ScienceEngineering, or a related field and three 3 years of experience in the job offered or related occupation.br br Experience must include three 3 years with each of the followingbr 1. Developing complex directrandom verification environment using Verilog, System Verilog, UVM, OVM.br 2. Modeling RTL design using CC programming language.br 3. Computer Architecture to implement simulation test bench in UVM.br 4. Defining and developing verification environment and implement comprehensive test plan.br 5. Digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology.br 6. Protocols such as Ethernet, PCIe, DDR, or AMBA protocols.br 7. Identifying bugs in architecture, functionality and performance using debug skills.br 8. Industrystandard simulators, revision control systems and regression systems.br 9. Scripting languages like Shell, Perl, Python.

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