Bachelors degree or foreign equivalent degree in Electrical and Electronic Engineering, Hardware Engineer or a related field, plus five years of progressive, postbaccalaureate experience working as a Staff Engineer, or a related occupation. Specific Skills Background, education, or experience must include 1.Static Timing signoff and associated Tools including Primetime and Tempus; 2.Synthesis and associated Tools including Design Compiler and RTL Compiler; 3.Formal Verification and associated Tools including Formality and Conformal LEC; 4.Constraints and Exceptions Development and Automation Across Various Modes Functional, Scan, MBIST; 5.Scripting, Automation and Flow Development using various Languages including TCL, Shell, PERL, and Python; 6.Constraints and Exceptions Checker Tools including Fishtail; 7.Signal Integrity Signoff in Static Timing Analysis; 8.HD Languages Verilog, System Verilog etc.; and 9.Debugging checktiming and QoR Issues in Designs.

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