The position also requires the ability to perform SystemVerilog modeling of analog design blocks; Mixedsignal verification of power management ICs; debugging of RTL code; and design verification at chiptop level.
Categories: eb3
The position also requires the ability to perform SystemVerilog modeling of analog design blocks; Mixedsignal verification of power management ICs; debugging of RTL code; and design verification at chiptop level.
0 Comments