Minimum education required Bachelors degree or the equivalent in Electrical Engineering or a related field.br br Minimum experience required 6 years of experience in the job offered or a related engineering occupation.br br Skills required Experience with RTL circuit design with Verilog for ASICSOC design. Experience with RTL circuit verification using SystemVerilog, or SVA, or VCS. Knowledge of image processing or digital signal processing. Experience with simulation modelling using CC programming language. Experience with physical back end including formal verification, timing closure, ECOs, static timing analysis, power analysis tools, library files. Experience with ShellPerlRuby or Excel Macro scripting. Experience with MIPI camera serial interface protocol. Experience with serial protocols. Employer will accept any amount of professional experience with the required skills.br br Telecommuting is permitted from any location in the U.S.
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