Must have at least 1 year of prior work experience in the followingbr 1. Development of Self checking testbench using System Verilog language.br 2. Development of verification testbench components or environments using UVM or OVM methodologies.br 3. Test plan development and test plan execution.br 4. Analyzing and debugging the failures in simulation using Synopsys VCS or Cadence IES tools.br 5. Coverage writing, coverage collection and improving coverage of the design under testbr 6. Automation using scripting languages Python or Perl.br br Employer will accept alternate combination of education and experience Bachelors degree in an accepted degree field and five 5 years of progressive experience in position or related occupation.br br Employer will accept any suitable combination of education, training, or experience.
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