SYNOPSYS, INC. – $126,464.00/Year

Requires Masters degree or foreign equivalent degree in Computer Engineering, ElectricalElectronic Engineering, Computer Science or a related field and six 6 months of experience supporting andor performing physical design implementation and verification.br br Education andor experience must include 1. RTL design tools; 2. Physical design and layout verification using EDA tools; 3. VerilogSystem Verilog; 4. RTL design, logic synthesis, floor planning, place route, CTS, STA, UPF, and chip finishing; 5. TCL scripting language; 6. Timing analysis and design optimization; 7. Low power multivoltage designs; 8. Troubleshooting physical design flows and issues; and 9. Developing methodologyflow scripts using TCL.