JUNIPER NETWORKS – $139,119.00/Year

48 months in the following Manufacturing defects and design process; IEEE standards for DFT architecture and testing; Design language coding i.e., Verilog VHDL; Design for Test DFT Electronic Design Automation EDA tool for architecture and testing; Competitive analysis of effective way of performing Fault Coverage; and PostSilicon debug and yield improvement of silicon. Telecommuting allowed.