Contd from above Masters degree or foreign equivalent in Electronic Engineering, Computer Engineering or a related field and 1 year of experience in design of digital logic hardware or a Bachelors degree or foreign equivalent in Electronic Engineering, Computer Engineering or a related field and 3 years of experience in design of digital logic hardware. Experience 1 year w Masters or 3 years wBachelors to include C, SystemC, and Register Transfer Level RTL design languages of VHDL and Verilog; Field Programmable Gate Array FPGA technology and architectures including memory and DSP configurations and key differentiators for high performance implementations; Application Specific Integrated Circuit ASIC technologies; RTL Simulation solution Siemens Questa; RTL synthesis solutions Intel Quartus Integrated Synthesis, Xilinx Vivado, Synopsys Design Compiler, Siemens Oasys, or Synopsys Synplify; and, Timing analysis associated with RTL synthesis using industrystandard Synopsys Design Constraints.br br Employer will accept any suitable combination of education, experience, or training.
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