Verilog; System Verilog; UVM Universal Verification Methodology; Serial Interface protocols for router design; Verification BFMs Bus Functional Models; Digital Design Verification.
Bachelors degree in Finance, Economics or a closely related field and three 3 years of experience in the job offered or as an FRC ETrader, STIR Trader, CoOp Intern or related role. Employer will accept Read more…
0 Comments