Bachelors degree in Computer Science, Computer Engineering, Electrical Engineering, or related field and completion of a universitylevel course, research project, internship, or thesis or one year of experience involving Verilog or VHDL skills; SystemVerilog; algorithms data structures; Verification and unit testing; at least one simulation tool Mentor, Synopsys or Cadence; Timing analysis and optimization; Python or BASH scripting; and FPGA or ASIC design process.
Categories: eb3
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