Employer will accept a Masters degree in Computer Science, Computer Software, Computer Engineering, Applied Sciences, Mathematics, Physics, or related field and 24 months of experience in the job offered or in a design engineering or computerrelated occupation.br br Experience must include 6 months of experience in each of the followingbr br 1. System Verilog OVMUVM DV experience;br 2. Python, Perl, or Shell Scripting;br 3. Assertions SVA or others;br 4. Digital ASICs design flows;br 5. C; andbr 6. Object Oriented Programming.
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