Experience in SerDes physical design, SoC level floorplanning, and scalable test chip framework design with multiple integrated Analog and Digital IPs. Will accept any suitable combination of education, training, or experience.
Categories: eb3
Experience in SerDes physical design, SoC level floorplanning, and scalable test chip framework design with multiple integrated Analog and Digital IPs. Will accept any suitable combination of education, training, or experience.
0 Comments