Must have at least 1 year of prior work experience in the followingbr 1. Developing UVM and System Verilog testbenches;br 2. Logic Design;br 3. Industry standard communication protocols;br 4. Scripting skills for verification automation;br 5. Verification management and revision control tools;andbr 6. State of the art verification techniques, including assertion and metricdriven verification.br br Employer will accept alternate combination of education and experience Masters degree in an accepted degree field and three 3 years of progressive, postbaccalaureate experience as Hardware Engineer or related occupation. Employer will accept any suitable combination of education, training, or experience.
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