For either combination of education and experience, employer requires two 2 years of experience in the following UVM, System Verilog, VHDL, or Verilog; Python, C, C, Perl, TCL, or Shell; coordination of technical projects associated with product development lifecycles, including determining technical priorities; CC; verification of GPU, CPU, SOC, or other complex IPs; RTL verification, functional verification or microprocessors, hardware verification, graphics IP architecture verification, memory verification IP, or design flowsmethodologies for chip verification; and EDA tools or CAD technology.br br Employer will accept any suitable combination of education, training, or experience.
Categories: eb3
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